1. Field of the Invention
This invention relates to the fabrication of electronic devices and, in particular, to fabrication procedures utilizing lithographic techniques.
2. Art Background
Trilevel resists have been utilized in the formation of electronic devices and are especially suitable for the lithographic definition of small features, i.e., features smaller than 2 .mu.m. These resists include an underlying layer generally deposited directly on the substrate being processed. (The substrate in this context is the semiconductor body including, if present, various levels of, for example, metallization, doped semiconductor material, and/or insulators.) Since the substrate typically does not have a planar surface, this layer is usually deposited with a thickness that is sufficient, despite the underlying irregularity, to present an essentially planar upper surface. An intermediary layer is then formed on this planarizing layer. The composition of the intermediary layer is chosen so that it is etched at least 5 times slower than the planarizing layer by a plasma that is capable of removing the underlying resist layer. A third layer (an overlying layer) that is delineable by exposure to radiation and by subsequent treatment with a suitable developing medium, is formed on the intermediary layer.
The trilevel resist is patterned by first delineating the overlying layer in the desired pattern. This pattern is then transferred to the intermediary layer through conventional techniques such as dry processing, e.g., reactive ion etching, causing an uncovering, in the desired pattern, of the underlying layer. The uncovered regions, generally of organic materials, are then removed with an oxygen plasma. Intermediary layers of materials such as silicon dioxide, that are essentially unaffected by an oxygen plasma, are employed to avoid its destruction during plasma processing and thus degradation of the transferred pattern.
Although the trilevel resist has proven to be an excellent expedient for producing fine features during semiconductor device fabrication, it does involve several discrete processing steps. Since there is always a desire to reduce processing steps and the associated costs, there has been a significant effort to develop a bilevel system yielding the advantages, i.e., planarization and high resolution, of a trilevel system. Attempts typically have been made to combine the attributes of the intermediary layer and the overlying layer into a single layer. To effect this combination, the resultant layer must be both delineable and also be at least 5 times more resistant than the underlying layer to the medium utilized to develop the underlying layer. Several materials have been reported as candidates, for use as this combined overlying material. For example, materials represented by the formulas ##STR1## have been reported in the literature. (See Regional Technical Conference, "Photopolymers Principles-Processes and Materials," J. M. Shaw et al, Nov. 8, 1982, Ellenville, N.Y. (for compound 1), 1983 International Symposium on Electron, Ion and Photon Beams, S. A. MacDonald, May 31, 1983, Los Angeles, Calif. (for compounds 2 and 3), and Journal of the Electrochemical Society, 130, Suzuki et al, page 1962 (1983), for the remaining compounds.) Although these materials are resistant to an oxygen plasma, each is not entirely acceptable for other reasons. For example, all these materials are negative resists. Although negative resists are not inherently undesirable, most of the masks presently utilized for exposing resists and, in particular, trilevel resists, have been developed for positive resists. Thus, the use of a negative resist would require a complete change in the mask sets being utilized to produce semiconductor devices. Although this change is possible, it is costly and would not be desired. Additionally, the material represented by formula (1) either lacks dimensional stability and tends to creep during processing for thick films, or is highly defective when utilized in a thin layer. Thus, one of the purposes for utilizing a multilayer resist--increased resolution--is lost.
As a result, although there is a strong incentive to develop a bilevel resist having the attributes of a trilevel configuration, each proposal has, as yet, not been entirely satisfactory.